US 7,541,636 B2
	Memory cell comprising one MOS transistor with an isolated body having a reinforced memory effect
Rossella Ranica, Grenoble (France); Alexandre Villaret, Grenoble (France); and Pascale Mazoyer, Domene (France)
Assigned to STMicroelectronics Crolles SAS, Crolles (France)
Filed on Jun. 30, 2006, as Appl. No. 11/479,421.
Claims priority of application No. 05 51836 (FR), filed on Jun. 30, 2005.
Prior Publication US 2007/0013030 A1, Jan. 18, 2007
Int. Cl. H01L 29/78 (2006.01)

U.S. Cl. 257—314  [257/E29.019; 257/E29.025; 438/294]

15 Claims

1. A memory cell with one transistor on a floating body region isolated by its lower surface by a junction, in which said junction is non-planar, further comprising an isolating ring around the floating body region, the isolating ring having an upper portion with a first width and a lower portion with a second width that is less than the first width, wherein said junction exhibits a peripheral upward protrusion at a level of the lower portion of the isolating ring.