| US 7,541,635 B2 | ||
| Semiconductor fabrication using a collar | ||
| Kevin Torek, Meridian, Id. (US); Kevin Shea, Boise, Id. (US); Niraj B. Rana, Boise, Id. (US); and Zhiping Yin, Boise, Id. (US) | ||
| Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
| Filed on Jul. 21, 2006, as Appl. No. 11/490,770. | ||
| Application 11/490770 is a division of application No. 10/788977, filed on Feb. 27, 2004, granted, now 7,109,089. | ||
| Prior Publication US 2006/0261395 A1, Nov. 23, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 27/108 (2006.01); H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—306 [257/E27.094] | 19 Claims |
| 1. An array of memory cells comprising:
a substrate;
a number of memory containers formed on the substrate, wherein a first memory container of the number of memory containers
is located a first distance, S, from a first adjacent memory container of the number of memory containers in a first direction
and wherein the first memory container is located a second distance, L, from a second adjacent memory container of the number
of memory containers in a second direction, wherein S is less than L; and
a collar comprised of silicon nitride and formed on external side walls of the number of memory containers, wherein the collar
formed on the external side walls is thicker than S/2 and thinner than L/2.
|