| US 7,541,624 B2 | ||
| Flat profile structures for bipolar transistors | ||
| Young-Kai Chen, Berkeley Heights, N.J. (US); Rose Fasano Kopf, Green Brook, N.J. (US); Wei-Jer Sung, Hsinchu (Taiwan); and Nils Guenter Weimann, Chatham, N.J. (US) | ||
| Assigned to Alcatel-Lucent USA Inc., Murray Hill, N.J. (US) | ||
| Filed on Jul. 21, 2003, as Appl. No. 10/624,038. | ||
| Prior Publication US 2005/0032323 A1, Feb. 10, 2005 | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 257—197 [257/200; 257/201; 257/592; 257/623] | 14 Claims |
| 1. An integrated circuit, comprising:
a substrate having a top surface;
collector, base, and emitter semiconductor layers of a bipolar transistor, the semiconductor layers forming a vertical sequence
on the substrate in which intrinsic portions of two of the semiconductor layers are sandwiched between the top surface of
the substrate and a remaining top one of the semiconductor layers, the base layer comprising an extrinsic portion that laterally
encircles a vertical portion of the top one of the semiconductor layers; and
a dielectric sidewall being interposed between the vertical portion of the top one of the semiconductor layers and the extrinsic
portion of the base layer; and
wherein the substrate includes a subcollector that forms an electrical contact for the collector layer, the entire subcollector
being located outside of the portion of the substrate that is vertically below part of the base layer.
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