| US 7,541,613 B2 | ||
| Methods for reducing within chip device parameter variations | ||
| Brent Alan Anderson, Jericho, Vt. (US); Shahid Ahmad Butt, Ossining, N.Y. (US); Allen H. Gabor, Katonah, N.Y. (US); Patrick Edward Lindo, Poughkeepsie, N.Y. (US); Edward Joseph Nowak, Essex Junction, Vt. (US); and Jed Hickory Rankin, South Burlington, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on May 08, 2008, as Appl. No. 12/117,014. | ||
| Application 12/117014 is a continuation of application No. 11/382489, filed on May 10, 2006, granted, now 7,393,703. | ||
| Prior Publication US 2008/0246097 A1, Oct. 09, 2008 | ||
| Int. Cl. H01L 23/58 (2006.01); H01L 21/66 (2006.01); H01L 21/00 (2006.01) | ||
| U.S. Cl. 257—48 [257/E21.524; 438/14; 438/11; 438/18] | 14 Claims |
| 1. An integrated circuit chip, comprising:
a multiplicity of virtual regions, at least two or more of said virtual regions having identically designed field effect transistors;
a reflectivity of light of a first region of said two or more virtual regions different from a reflectivity of light of a
second region of said two or more virtual regions;
first field effect transistors in said first region of said two or more virtual regions having physical polysilicon gate lengths
that are different from physical polysilicon gate lengths of second field effect transistors in said second region of said
two or more virtual regions, said first and second field effect transistors identically designed; and
wherein a value of a functional device parameter of said first field effect transistors in said first region of said two or
more virtual regions is the same as a value of a same functional device parameter of said second field effect transistors
in said second region of said two or more virtual regions.
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