forming a gate insulation film on a semiconductor substrate in which element separation regions are formed;

depositing a gate lower layer material on the semiconductor substrate via the gate insulation film;

depositing a gate upper layer material, which comprises a material different from the gate lower layer material, on the gate lower layer material;

forming a gate comprising a gate upper layer and a gate lower layer by selectively processing the gate upper layer material and the gate lower layer material;

forming gate side walls on the side surface portions of the gate;

forming a first impurity implantation region by implanting ions into the semiconductor substrate using the gate side walls as a mask;

forming a source/drain diffusion layer from the first impurity implantation region by carrying out a thermal diffusion treatment;

removing the gate sides walls, and thereafter increasing the size of the gate upper layer in a horizontal direction with respect to the semiconductor substrate by carrying out a chemical reaction processing treatment to which the gate upper layer has a higher reaction speed than the gate lower layer;

forming a second impurity implantation region by implanting ions into the semiconductor substrate using the gate upper layer as a mask; and

forming an extension region diffusion layer from the second impurity implantation region by carrying out a thermal diffusion treatment.