| US 7,541,294 B2 | ||
| Semiconductor package and semiconductor package mounting method | ||
| Kenichi Shirasaka, Hamamatsu (Japan) | ||
| Assigned to Yamaha Corporation, (Japan) | ||
| Filed on Nov. 14, 2005, as Appl. No. 11/273,666. | ||
| Application 10/732309 is a division of application No. 10/119315, filed on Apr. 10, 2002, granted, now 6,861,282. | ||
| Application 11/273666 is a continuation of application No. 10/732309, filed on Dec. 11, 2003, granted, now 6,979,910. | ||
| Claims priority of application No. P2001-115380 (JP), filed on Apr. 13, 2001; and application No. P2002-079371 (JP), filed on Mar. 20, 2002. | ||
| Prior Publication US 2006/0060948 A1, Mar. 23, 2006 | ||
| Int. Cl. H01L 21/31 (2006.01); H01L 21/469 (2006.01); H01L 23/04 (2006.01); H01L 32/50 (2006.01); H01L 23/544 (2006.01) | ||
| U.S. Cl. 438—765 [257/797; 257/730; 257/786] | 6 Claims |
| 1. A semiconductor package having a polygon shaped top surface, said semiconductor package comprising:
a chamfered portion of at least one corner of said semiconductor package; and
a display section provided on a surface to be a top surface when said semiconductor package is mounted on a substrate, said
display section having an identification portion formed in a vicinity of a specific corner of said semiconductor package and
having a shape different from the other corners so as to make the specific corner distinguishable from the other corners,
wherein said identification portion is dimensioned such that verification of the semiconductor package can be carried out
by a plurality of different assemblers without altering a threshold value used for the verification.
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