US 7,541,252 B2
Methods of fabricating a semiconductor device including a self-aligned cell diode
Sung-Ho Eun, Ansan-si (Korea, Republic of); Jae-Hee Oh, Seongnam-si (Korea, Republic of); Jae-Hyun Park, Yongin-si (Korea, Republic of); Jung-In Kim, Seoul (Korea, Republic of); Seung-Pil Ko, Suwon-si (Korea, Republic of); and Yong-Tae Oh, Seoul (Korea, Republic of)
Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of)
Filed on Jun. 29, 2007, as Appl. No. 11/770,764.
Claims priority of application No. 10-2006-0110549 (KR), filed on Nov. 09, 2006.
Prior Publication US 2008/0113469 A1, May 15, 2008
Int. Cl. H01L 21/20 (2006.01)
U.S. Cl. 438—381  [257/E21.364; 257/E21.366] 19 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, comprising:
forming a conductive layer on a semiconductor substrate;
forming an insulating layer on the conductive layer;
patterning the insulating layer and the conductive layer to form a plurality of stacked structures separated by isolations trenches, wherein each of the stacked structures includes a patterned portion of the conductive layer which defines a word line and a corresponding patterned portion of the insulating layer stacked on the word line;
forming an isolation layer that fills the isolation trenches;
forming a cell contact hole in each of the patterned portions of the insulating layer such that the cell contact hole is self-aligned between the isolation trenches and with a corresponding word line so as to expose the corresponding word line; and
forming a cell diode in the cell contact hole.