| US 7,541,236 B2 | ||
| Method for manufacturing semiconductor device | ||
| Koji Takahashi, Omura (Japan); and Shinichi Nakagawa, Kawasaki (Japan) | ||
| Assigned to Fujitsu Limited, Kawasaki (Japan) | ||
| Filed on Dec. 23, 2004, as Appl. No. 11/19,549. | ||
| Claims priority of application No. 2004-198888 (JP), filed on Jul. 06, 2004. | ||
| Prior Publication US 2006/0008995 A1, Jan. 12, 2006 | ||
| Int. Cl. H01L 21/8238 (2006.01) | ||
| U.S. Cl. 438—201 [438/258; 257/E21.689] | 13 Claims |
| 1. A method for manufacturing a semiconductor device, comprising the steps of:
forming a nonvolatile memory cell, an nMOS transistor, and a pMOS transistor on a surface of a semiconductor substrate;
forming an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor;
forming, in the interlayer insulation film, a plurality of contact holes exposing respectively a control gate of the nonvolatile
memory cell, a source or a drain of the nMOS transistor, and a source or drain of the pMOS transistor; and
forming a single-layer first wiring connecting the control gate to the sources or the drains of the nMOS transistor and the
pMOS transistor, and a single-layer second wiring connecting the sources or the drains of the nMOS transistor and the pMOS
transistor to each other which sources or the drains are not connected to said first wiring, via the plurality of the contact
holes in a same layer,
wherein the semiconductor device has an embedded structure.
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