| US 7,541,231 B1 | ||
| Integration of SiGe NPN and vertical PNP devices on a substrate | ||
| Paul D. Hurwitz, Irvine, Calif. (US); Kenneth M. Ring, Tustin, Calif. (US); Chun Hu, Irvine, Calif. (US); and Amol Kalburge, Irvine, Calif. (US) | ||
| Assigned to Newport Fab, LLC, Newport Beach, Calif. (US) | ||
| Filed on Mar. 17, 2005, as Appl. No. 11/84,391. | ||
| Application 11/084391 is a continuation of application No. 10/821425, filed on Apr. 09, 2004, granted, now 6,933,202. | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 21/338 (2006.01); H01L 31/0328 (2006.01); H01L 31/0336 (2006.01); H01L 31/072 (2006.01); H01L 31/109 (2006.01) | ||
| U.S. Cl. 438—170 [257/197; 257/565; 257/552] | 17 Claims |
| 1. A structure comprising:
an insulating layer situated over an NPN region and a PNP region of a substrate;
a buffer layer situated on said insulating layer;
an opening in said buffer layer and said insulating layer in said NPN region;
a semiconductor layer situated on said buffer layer and in said opening, said semiconductor layer having a first portion situated
in said opening and a second portion situated on said buffer layer in said PNP region;
wherein said first portion of said semiconductor layer forms a base of an NPN device and said second portion of said semiconductor
layer forms an emitter of a PNP device.
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