| US 7,541,225 B2 | ||
| Method of manufacturing a thin film transistor array panel that includes using chemical mechanical polishing of a conductive film to form a pixel electrode connected to a drain electrode | ||
| Bum-Ki Baek, Gyeonggi-do (Korea, Republic of); and Hyuk-Jin Kim, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Jan. 13, 2006, as Appl. No. 11/332,076. | ||
| Claims priority of application No. 10-2005-0003680 (KR), filed on Jan. 14, 2005. | ||
| Prior Publication US 2006/0194376 A1, Aug. 31, 2006 | ||
| Int. Cl. H01L 21/84 (2006.01) | ||
| U.S. Cl. 438—149 [438/158; 438/633; 257/E21.7] | 20 Claims |
| 1. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a substrate;
forming a passivation layer on the source electrode and the drain electrode;
forming a photoresist film on the passivation layer;
selectively etching the passivation layer using the photoresist film as a mask;
forming a conductive film on the remaining portion of the photoresist film and a portion of the gate and the drain electrode;
and
removing the photoresist film and the conductive film using a chemical mechanical polishing process to form a pixel electrode
connected to the drain electrode.
|