| US 7,541,209 B2 | ||
| Method of forming a device package having edge interconnect pad | ||
| Charles C Haluzak, Corvallis, Oreg. (US); Chien-Hua Chen, Corvallis, Oreg. (US); and David M Craig, Albany, Oreg. (US) | ||
| Assigned to Hewlett-Packard Development Company, L.P., Houston, Tex. (US) | ||
| Filed on Oct. 14, 2005, as Appl. No. 11/251,412. | ||
| Prior Publication US 2007/0087462 A1, Apr. 19, 2007 | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 438—48 [438/51] | 11 Claims |
| 1. A method for forming an edge interconnect pad to a MEMS device package, comprising:
forming an array of MEMS devices overlaying at least one conductive via that electrically connects to an underlying layer,
wherein the underlying layer is a CMOS layer;
depositing, by way of a damascene process, a conductive material on a substrate that is coplanar with the array of MEMS devices,
the conductive material coupling to the at least one conductive via; and
covering the array of MEMS devices and the conductive material with a passivation layer, wherein the cover includes a conductive
post that couples to the conductive material deposited on the substrate, the conductive post providing an electrical connection
by way of the topside of the cover.
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