| US 7,540,427 B2 | ||
| IC tag | ||
| Masateru Yamakage, Matsudo (Japan); Katsuhisa Taguchi, Koshigaya (Japan); Tomoyuki Hasegawa, Saitama (Japan); and Toru Takahara, Saitama (Japan) | ||
| Assigned to Lintec Corporation, Tokyo (Japan) | ||
| Appl. No. 10/514,495 PCT Filed May 14, 2003, PCT No. PCT/JP03/06026 § 371(c)(1), (2), (4) Date Jul. 01, 2005, PCT Pub. No. WO03/098545, PCT Pub. Date Nov. 27, 2003. |
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| Claims priority of application No. 2002-140535 (JP), filed on May 15, 2002. | ||
| Prior Publication US 2006/0273179 A1, Dec. 07, 2006 | ||
| Int. Cl. G06K 19/06 (2006.01) | ||
| U.S. Cl. 235—492 [235/435; 235/488] | 4 Claims |
| 1. An IC tag which has a structure comprising a first adhesive layer laminated on a surface of a substrate sheet, an electronic
circuit and an IC chip connecting both ends of a line of the electronic circuit, both the electronic circuit and the IC chip
being formed on a surface of the first adhesive layer, and a second adhesive layer laminated for covering the electronic circuit
and the IC chip, wherein a release agent layer is further formed at positions corresponding to both separated end sections
of the electronic circuit and located at the interface between the substrate sheet and the first adhesive layer, but is not
formed at positions corresponding to the center section of the electronic circuit,
wherein the release agent layer is formed to cover a range of 20 to 90 percent of an area surrounded by an outside circumference
of the electronic circuit throughout the first adhesive layer such that the electronic circuit is rendered electrically inoperable
when the substrate is peeled off from the IC tag.
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