| US 7,539,953 B1 | ||
| Method and apparatus for interfacing instruction processors and logic in an electronic circuit modeling system | ||
| Shay Ping Seng, San Jose, Calif. (US); Jonathan B. Ballagh, Boulder, Colo. (US); Roger B. Milne, Boulder, Colo. (US); and Bradley L. Taylor, Santa Cruz, Calif. (US) | ||
| Assigned to Xilinx, Inc., San Jose, Calif. (US) | ||
| Filed on Dec. 05, 2006, as Appl. No. 11/633,977. | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—1 [716/3; 716/17] | 20 Claims |
| 1. A method of circuit design, comprising:
specifying a model having at least one processor, at least one logic block, and at least one shared memory, the at least one
shared memory providing an interface between the at least one processor and the at least one logic block;
associating at least one shared memory with the at least one processor; and
automatically generating a memory-map associated with the at least one shared memory and a bus adapter for coupling the memory-map
to the at least one processor.
|