US 7,539,927 B2
High speed hardware implementation of modified Reed-Solomon decoder
Shuenn-Gi Lee, Hsinchu (Taiwan); Shin-Lin Shieh, Chin-Men (Taiwan); and Wern-Ho Sheen, Chiayi (Taiwan)
Assigned to Industrial Technology Research Institute, Hsinchu (Taiwan)
Filed on Apr. 14, 2005, as Appl. No. 11/105,420.
Prior Publication US 2006/0236212 A1, Oct. 19, 2006
Int. Cl. H03M 13/15 (2006.01)
U.S. Cl. 714—784 27 Claims
OG exemplary drawing
 
1. A decoder suitable for use in a digital communications system utilizing an RS(n′, k′) code modified from an RS(n, k) code, wherein the decoder receives n′-symbol vectors each including k′ message symbols and r′=n′−k′ parity symbols and decodes the n′-symbol vectors to correct errors therein, wherein n, k, n′, and k′ are integers, and k′<n′<n, k′<k <n, and wherein the decoder stores one erasure locator polynomial σ0(x), the decoder comprising:
a syndrome calculator for receiving the n′-symbol vectors and for calculating syndromes of each n′-symbol vector, wherein the i-th syndrome Si of one n′-symbol vector R′, (rn′−1, rn′−2, . . . , r0), is Si=Rsi+1) for i=0, 1, . . . , n−k−1, wherein Rs(x)=rn′−1xn′−1+rn′−2xn′−2+ . . . +r0;
an index adjustment circuit for generating an adjusted error/erasure locator polynomial σ(x) and an adjusted error/erasure evaluator polynomial ω(x) based on the syndromes calculated by the syndrome calculator;
a memory device for storing the one erasure locator polynomial σ0(x) and a look-up table; and
means for finding the locations and values of the errors in each n′-symbol vector based on the adjusted error/erasure locator polynomial σ(x) and the adjusted error/erasure evaluator polynomial ω(x), using the look-up table.