| US 7,539,911 B2 | ||
| Test mode for programming rate and precharge time for DRAM activate-precharge cycle | ||
| Robert Perry, Cary, N.C. (US); Norbert Rehm, Apex, N.C. (US); Jan Zieleman, Cary, N.C. (US); and Rath Ung, Apex, N.C. (US) | ||
| Assigned to Infineon Technologies AG, Neubiberg (Germany) | ||
| Filed on May 27, 2005, as Appl. No. 11/138,462. | ||
| Prior Publication US 2006/0282718 A1, Dec. 14, 2006 | ||
| Int. Cl. G11C 29/00 (2006.01) | ||
| U.S. Cl. 714—718 [365/201; 360/53] | 43 Claims |
| 1. A method for testing a memory device comprising:
a. programming for storage in a storage element in the memory device values for a rate and a precharge time for activate and
precharge signals of an activate-precharge cycle of the memory device;
b. generating activate and precharge signals with respect to an internal clock of the memory device based on the programmed
values for rate and precharge time;
c. coupling the activate and precharge signals to a wordline of the memory device; and
d. testing one or more functions of the memory device on said wordline during the activate-precharge cycle.
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