| US 7,539,884 B2 | ||
| Power-gating instruction scheduling for power leakage reduction | ||
| Yi-Ping You, Taichung County (Taiwan); Chung Wen Huang, Chiayi County (Taiwan); Jeng Kuen Lee, Tainan (Taiwan); Chi-Lung Wang, Hsinchu (Taiwan); and Kuo Yu Chuang, Yilan County (Taiwan) | ||
| Assigned to Industrial Technology Research Institute, Hsinchu (Taiwan) | ||
| Filed on Jul. 27, 2006, as Appl. No. 11/493,765. | ||
| Claims priority of application No. 94147221 A (TW), filed on Dec. 29, 2005. | ||
| Prior Publication US 2007/0157044 A1, Jul. 05, 2007 | ||
| Int. Cl. G06F 1/32 (2006.01); G06F 1/00 (2006.01); G06F 9/45 (2006.01) | ||
| U.S. Cl. 713—320 [713/300; 713/323; 713/324; 717/155; 717/161] | 12 Claims |
| 1. A method of power-gating instruction scheduling for power leakage reduction, comprising:
receiving a program;
generating a control-flow graph by dividing the program into a plurality of blocks and linking the blocks according to the
program, wherein the control-flow graph contains control commands;
analyzing utilization of power-gated components of a processor executing the program;
generating first power-gating instruction placement based on the control-flow graph and the utilization of the power-gated
components, the first power-gating instruction placement comprising a plurality of power-off instructions and a plurality
of power-on instructions to shut down inactive components;
generating second power-gating instruction placement by modifying the first power-gating instruction placement, wherein the
second power-gating instruction placement comprises compound power-off instructions and compound power-on instructions generated
by combining the combinable power-off instructions and combining the combinable power-on instructions respectively;
inserting power-gating instructions into the program according to the second power-gating instruction placement; and
executing the program by the processor.
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