US 7,539,879 B2
	Register file gating to reduce microprocessor power dissipation
Andrei Terechko, Eindhoven (Netherlands); and Manish Garg, Eindhoven (Netherlands)
Assigned to NXP B.V., Eindhoven (Netherlands)
Appl. No. 10/561,627 PCT Filed Dec. 03, 2003, PCT No. PCT/IB03/05608 § 371(c)(1), (2), (4) Date Dec. 19, 2005, PCT Pub. No. WO2004/051449, PCT Pub. Date Jun. 17, 2004.
Claims priority of provisional application 60/430883, filed on Dec. 04, 2002.
Prior Publication US 2006/0168463 A1, Jul. 27, 2006
Int. Cl. G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 1/32 (2006.01)

U.S. Cl. 713—300  [713/320; 713/322; 713/324]

21 Claims

1. A circuit arrangement comprising: a register file partitioned into a plurality of banks each bank including at least one register and at least one clock input, address input and data input; enable logic coupled to the register file and configured to selectively disable at least one unused bank from among the plurality of banks by gating off the clock, address and data inputs thereof; and a support register configured to store information, including status information unrelated to power dissipation control, and to be updated responsive to execution of a power control instruction by a processor.