a mother board including an application block and a first communication block;

a core board including one or more devices which simulate, by software, peripheral devices of the built-in microcomputer so as to execute an input or output process, the core board further including a computing block and a second communication block;

a peripheral component interconnect (PCI) bus coupling said mother board and said core board;

an interface board including a port assignment conversion board, a plurality of standard circuits, and a plurality of facility boards which are associated with hardware of said electronic control unit, said standard circuits and facility boards being selectable by said port assignment conversion board, and said port assignment conversion board being coupled to said core board via a harness; and

a bus controller in said computing block interposed between said first communication block in said mother board and each of said one or more devices,

an internal memory in said computing block coupled to said bus controller over a first internal bus, wherein,

said first communication block included in said mother board and said bus controller are coupled to each other over said PCI bus, and said bus controller and each of said one or more devices are coupled to each other over a second internal bus,

said first communication block and each of said one or more devices transfer data to or from each other according to two transfer techniques,

wherein a first one of the two transfer techniques transfers a first portion of the data by way of said PCI bus, bus controller, and the second internal bus without using said internal memory, the first one of the two transfer techniques being invoked for acquiring input information on the mother board during a first action of an application, and

a second one of the two transfer techniques transfers a second portion of the data via said internal memory, wherein the second portion of the data from one of said one or more devices is stored in said internal memory via said first internal bus and said bus controller, and the second portion of the data stored in said internal memory is transmitted to said first communication block via said bus controller concurrently, wherein the second transfer technique is carried out before a second action of the application responsive to an interrupt request from the core board to the mother board.