US 7,539,097 B2
Optical disk device
Youichi Ogura, Osaka (Japan); Toshihiko Takahashi, Osaka (Japan); Teruhiko Izumi, Osaka (Japan); Shinichi Konishi, Nara (Japan); Hironori Deguchi, Osaka (Japan); and Takamasa Sakai, Osaka (Japan)
Assigned to Panasonic Corporation, Osaka (Japan)
Filed on Sep. 26, 2005, as Appl. No. 11/234,212.
Claims priority of application No. 2004-280109 (JP), filed on Sep. 27, 2004.
Prior Publication US 2006/0077828 A1, Apr. 13, 2006
Int. Cl. G11B 20/00 (2006.01)
U.S. Cl. 369—47.19  [369/59.19] 19 Claims
OG exemplary drawing
 
1. An optical disk device comprising:
a first photodetector for detecting a light from an optical recording medium on which address information exists intermittently in an embossed area, said first photodetector being divided into four parts by a track direction axis and a radial direction axis that is perpendicular to the track direction axis;
an optical difference signal detection circuit for adding, among outputs from said first photodetector which have been current-to-voltage converted, the outputs corresponding to areas parallel to the track direction axis, and detecting a difference between the respective added values;
an amplitude adjustment circuit for adjusting the amplitude of an output signal of said optical difference signal detection circuit;
a clock generation circuit for generating, from the output signal of the optical difference signal detection circuit, a sampling clock having a frequency that is synchronized with digital data recorded on the optical recording medium;
a first analog-to-digital converter for converting an output signal of said amplitude adjustment circuit into a digital sampling signal according to the sampling clock;
an address polarity information detection circuit for detecting a peak envelope signal from the digital sampling signal, and comparing the peak envelope signal with a predetermined threshold value to detect address polarity information, wherein said address polarity information detection circuit comprises
a zone peak detection circuit for detecting an amount of peak in an arbitrary zone, from the digital sampling signal,
a first high-pass noise removal circuit for removing a high-pass noise component from an output signal of said zone peak detection circuit to detect the peak envelope signal,
a first low-pass variation component extraction circuit for extracting a low-pass variation component from an output signal of said first high-pass noise removal circuit,
a first threshold detection circuit for adding an arbitrary offset level to an output signal of said first low-pass variation component extraction circuit, and
a signal polarity determination circuit for comparing the output signal of said first high-pass noise removal circuit with the output signal of said first threshold detection circuit to generate the address polarity information, said signal polarity determination circuit includes a spike removal circuit for removing spike pulses that deteriorate continuity of the address polarity information, and a polarity signal mask circuit for enabling the address polarity information in a position where presence of the address information is estimated; and
an address position information detection circuit for detecting a bottom envelope signal from the digital sampling signal, detecting signal amplitude information from a difference in amplitudes between the peak envelope signal and the bottom envelope signal, and comparing the signal amplitude information with a predetermined threshold value, thereby detecting address position information, wherein said address position information detection circuit comprises
a zone bottom detection circuit for detecting the amount of bottom in an arbitrary zone, from the digital sampling signal,
a second high-pass noise removal circuit for removing a high-pass noise component from an output signal of said zone bottom detection circuit to detect the bottom envelope signal,
a second low-pass variation component extraction circuit for extracting a low-pass variation component from an output signal of said second high-pass noise removal circuit,
a signal amplitude detection circuit for detecting the signal amplitude information from a difference between the output signal of said first high-pass noise removal circuit and the output signal of said second high-pass noise removal circuit,
an amplitude low-pass variation detection circuit for extracting the amplitude low-pass variation component information from a difference between the output signal of said first low-pass variation component extraction circuit and the output signal of said second low-pass variation component extraction circuit,
a second threshold detection circuit for adding an arbitrary offset level to an output signal of said amplitude low-pass variation detection circuit, and
an address position detection circuit for comparing the output signal of said signal amplitude detection circuit with the output signal of said second threshold detection circuit to generate the address position information, said address position detection circuit includes a spike removal circuit for removing spike pulses that deteriorate continuity of the address position information, and an address position information mask circuit for enabling the address position information in a position where presence of the address information is estimated.