| US 7,539,076 B1 | ||
| Variable data width memory systems and methods | ||
| Hemanshu Vernenker, Austin, Tex. (US); Margaret Tait, Austin, Tex. (US); Christopher Hume, Austin, Tex. (US); Nhon Nguyen, Austin, Tex. (US); Allen White, Austin, Tex. (US); Tim Swensen, Mountain View, Calif. (US); Sam Tsai, Milpitas, Calif. (US); and Steve Eplett, Fremont, Calif. (US) | ||
| Assigned to Lattice Semiconductor Corporation, Hillsboro, Oreg. (US) | ||
| Filed on Oct. 01, 2007, as Appl. No. 11/865,556. | ||
| Application 11/865556 is a division of application No. 10/974453, filed on Oct. 25, 2004, granted, now 7,307,912. | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 8/00 (2006.01); G11C 7/00 (2006.01); G11C 7/10 (2006.01) | ||
| U.S. Cl. 365—230.05 [365/189.02; 365/189.03; 365/189.05; 365/189.14; 365/189.15; 365/189.16; 365/189.17; 365/189.18; 365/230.06] | 20 Claims |
| 1. An integrated circuit comprising:
a memory array;
a first port adapted to read data associated with the first port from the memory array and to write data associated with the
first port to the memory array; and
a second port adapted to read data associated with the second port from the memory array and to write data associated with
the second port to the memory array,
wherein the first port is further adapted to write data associated with the second port through the first port to the memory
array.
|