| US 7,539,075 B2 | ||
| Implementation of a fusing scheme to allow internal voltage trimming | ||
| Jennifer Faye Huckaby, Raleigh, N.C. (US); George William Alexander, Durham, N.C. (US); Steven Michael Baker, Morrisville, N.C. (US); and David SuitWai Ma, Cary, N.C. (US) | ||
| Assigned to Infineon Technologies AG, Munich (Germany) | ||
| Filed on Sep. 24, 2007, as Appl. No. 11/860,332. | ||
| Application 11/860332 is a division of application No. 11/142023, filed on Jun. 01, 2005, granted, now 7,277,350. | ||
| Prior Publication US 2008/0008012 A1, Jan. 10, 2008 | ||
| Int. Cl. G11C 5/14 (2006.01) | ||
| U.S. Cl. 365—226 [365/189.07] | 13 Claims |
| 1. A method for adjusting a trim setting used to trim a plurality of internally generated voltages of an integrated circuit,
comprising:
(a) receiving a target digital value for each of the plurality of internally generated voltages;
(b) comparing the target digital value to a current digital value for each of the plurality of internally generated voltages;
(c) adjusting the trim setting, for each of the plurality of internally generated voltages, based on a difference if the comparison
indicates that the difference between the target digital value and the current digital value is greater than an allowable
threshold; and
(d) repeating steps (b) and (c) for each of the plurality of internally generated voltages until the difference between the
target digital value and the current digital value is less than or equal to the allowable threshold; whereby the plurality
of internally generated voltages are each trimmed independently of each other according to steps (a) through (d).
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