| US 7,539,071 B2 | ||
| Semiconductor device with a relief processing portion | ||
| Tomohiro Kurozumi, Kyoto (Japan); Yasuhiro Agata, Osaka (Japan); Osamu Ichikawa, Osaka (Japan); and Shintaro Nagai, Kanagawa (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on May 31, 2007, as Appl. No. 11/806,308. | ||
| Claims priority of application No. 2006-152200 (JP), filed on May 31, 2006. | ||
| Prior Publication US 2007/0280015 A1, Dec. 06, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—200 [365/201; 365/221; 365/225.7] | 65 Claims |
| 1. A semiconductor device comprising:
a plurality of redundant memories, each of the plurality of redundant memories including a plurality of memory cells, being
relievable when a defective cell exists in the memory cells, and being operable independently of each other;
a relief processing portion wherein when at least one of the plurality of redundant memories has a defective cell, the relief
processing portion stores relief information for relieving the redundant memory and performs processing of relieving the redundant
memory, wherein
the relief information is stored in the relief information processing portion serially and is shared by the plurality of redundant
memories.
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