| US 7,538,602 B2 | ||
| Semiconductor integrated circuit with stepped-down voltage generating circuit | ||
| Atsushi Takeuchi, Kawasaki (Japan) | ||
| Assigned to Fujitsu Microelectronics Limited, Tokyo (Japan) | ||
| Filed on Jan. 11, 2007, as Appl. No. 11/651,966. | ||
| Application 11/651966 is a division of application No. 11/127153, filed on May 12, 2005, granted, now 7,336,108, filed on Feb. 26, 2008. | ||
| Application 11/127153 is a continuation of application No. PCT/JP2003/008212, filed on Jun. 27, 2003. | ||
| Prior Publication US 2007/0109036 A1, May 17, 2007 | ||
| Int. Cl. G05F 3/16 (2006.01); H02M 3/16 (2006.01) | ||
| U.S. Cl. 327—543 [327/541] | 4 Claims |
| 3. A semiconductor integrated circuit, comprising:
a voltage generating circuit configured to generate a predetermined voltage;
an NMOS transistor configured to receive at a gate node thereof the predetermined voltage generated by said voltage generating
circuit, to receive at a drain node thereof an external power supply voltage, and to generate at a source node thereof a stepped-down
voltage by reducing the external power supply voltage in response to the predetermined voltage; and
a PMOS transistor, provided between the drain node of said NMOS transistor and the external power supply voltage, configured
to receive at a gate node thereof a power-down signal indicative of a power-down mode,
a circuit configured to clamp the gate node of said NMOS transistor to a ground voltage in response to the power-down signal
indicating the power-down mode, wherein the predetermined voltage applied to the gate node of the NMOS transistor is set to
LOW in response to a HIGH state of the power-down signal applied to the gate node of the PMOS transistor.
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