| US 7,538,593 B2 | ||
| Circuit and method to convert a single ended signal to duplicated signals | ||
| Prabhat Agarwal, Calcutta (India); Mayank Goel, Bangalor (India); and Pradip Mandal, Kharagpur (India) | ||
| Assigned to Infineon Technologies AG, Munich (Germany) | ||
| Filed on Feb. 23, 2007, as Appl. No. 11/710,270. | ||
| Prior Publication US 2008/0204096 A1, Aug. 28, 2008 | ||
| Int. Cl. G06F 1/04 (2006.01) | ||
| U.S. Cl. 327—257 [327/258; 327/295] | 13 Claims |

| 1. A circuit to provide duplicate signals of a signal and invert one of the duplicate signals, the circuit comprising two paths, each of the two paths comprising a plurality of stages with the number of stages in each of the two paths being the same; a first path of the two paths comprising a buffer stage followed by at least one inverter stage and a second path of the two paths comprising only inverter stages; the buffer stage comprising a first pair of transistors comprising a first transistor of a first category operatively connected to a first transistor of a second category with their channel connections being connected in series, wherein the at least one inverter stage is configured to have a high impedance output state if an input to the buffer stage and an input to the at least one inverter stage does not comprise the same logical state. |