| US 7,538,576 B2 | ||
| Non-volatile look-up table for an FPGA | ||
| John McCollum, Saratoga, Calif. (US); Gregory Bakker, San Jose, Calif. (US); and Jonathan Greene, Palo Alto, Calif. (US) | ||
| Assigned to Actel Corporation, Mountain View, Calif. (US) | ||
| Filed on Sep. 20, 2007, as Appl. No. 11/858,341. | ||
| Application 11/858341 is a division of application No. 11/551973, filed on Oct. 23, 2006, granted, now 7,321,237. | ||
| Application 11/551973 is a continuation of application No. 11/026336, filed on Dec. 29, 2004, granted, now 7,129,748, filed on Oct. 31, 2006. | ||
| Prior Publication US 2008/0007293 A1, Jan. 10, 2008 | ||
| Int. Cl. G06F 7/38 (2006.01); H03K 19/177 (2006.01) | ||
| U.S. Cl. 326—40 [326/38; 326/41] | 6 Claims |
| 1. A non-volatile-memory-transistor based lookup table for an FPGA including:
a multiplexer having a plurality of address inputs, a plurality of data inputs, and an output;
a plurality of multiplexer input circuits, each multiplexer input coupled to a different one of the data inputs of the multiplexer
and including:
a first n-channel transistor having a drain coupled to a voltage potential, a gate, and a source;
a second n-channel transistor having a drain coupled to the source of the first n-channel transistor, a gate, and a source
coupled to ground;
a first non-volatile memory cell having an output coupled to the gate of the first n-channel transistor;
a second non-volatile memory cell having an output coupled to the gate of the second n-channel transistor; n-channel transistors coupled to each of the data inputs of the multiplexer;
a sense amplifier coupled to the output of the multiplexer.
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