| US 7,538,441 B2 | ||
| Chip with power and signal pads connected to power and signal lines on substrate | ||
| Hideho Inagawa, Yokohama (Japan) | ||
| Assigned to Canon Kabushiki Kaisha, Tokyo (Japan) | ||
| Filed on Jun. 19, 2007, as Appl. No. 11/765,185. | ||
| Application 11/765185 is a division of application No. 11/061438, filed on Feb. 22, 2005, granted, now 7,259,467. | ||
| Claims priority of application No. 2004-047408 (JP), filed on Feb. 24, 2004; and application No. 2005-033018 (JP), filed on Feb. 09, 2005. | ||
| Prior Publication US 2007/0235874 A1, Oct. 11, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 23/48 (2006.01); H01R 9/00 (2006.01) | ||
| U.S. Cl. 257—784 [257/786; 361/772; 361/773; 361/777] | 12 Claims |
| 1. A semiconductor integrated circuit device comprising:
a semiconductor chip having wire bonding pads arranged at a periphery of a semiconductor integrated circuit unit; and
a package encapsulating the semiconductor chip and having lines connected via bonding wires to the wire bonding pads,
wherein the wire bonding pads comprise signal pads and power supply pads, and are arranged in a plurality of rows along the
periphery of the semiconductor chip, wherein all of the power supply pads of the wire bonding pads are for supplying power
to the semiconductor integrated circuit unit and are disposed in an innermost area of the plurality of rows, and
wherein power supply lines are led out from the respective power supply pads, and have widths not less than widths of the
power supply pads.
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