| US 7,538,433 B2 | ||
| Semiconductor device | ||
| Koji Takemura, Osaka (Japan); Hiroshige Hirano, Nara (Japan); Yutaka Itoh, Kyoto (Japan); Hikari Sano, Hyogo (Japan); Masao Takahashi, Kyoto (Japan); and Koji Koike, Osaka (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Jun. 15, 2006, as Appl. No. 11/452,957. | ||
| Claims priority of application No. 2005-176824 (JP), filed on Jun. 16, 2005. | ||
| Prior Publication US 2007/0001308 A1, Jan. 04, 2007 | ||
| Int. Cl. H01L 23/52 (2006.01) | ||
| U.S. Cl. 257—750 [257/774] | 20 Claims |
| 1. A semiconductor device including at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor
substrate, the semiconductor device comprising:
a seal ring provided at the outer periphery of a chip region of the semiconductor substrate; and
a chip strength reinforcement provided in part of the chip region near the seal ring, wherein
the chip strength reinforcement is made of a plurality of dummy wiring structures and
each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including
only one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.
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