| US 7,538,390 B2 | ||
| Semiconductor device with PMOS and NMOS transistors | ||
| Junli Wang, Kanagawa (Japan); Toyotaka Kataoka, Kanagawa (Japan); and Masaki Saito, Tokyo (Japan) | ||
| Assigned to Sony Corporation, Tokyo (Japan) | ||
| Filed on Sep. 30, 2005, as Appl. No. 11/241,108. | ||
| Claims priority of application No. P2004-294562 (JP), filed on Oct. 07, 2004. | ||
| Prior Publication US 2006/0076622 A1, Apr. 13, 2006 | ||
| Int. Cl. H01L 29/94 (2006.01); H01L 21/8238 (2006.01) | ||
| U.S. Cl. 257—347 [257/350; 257/616; 438/199; 438/285; 438/479; 438/517] | 7 Claims |
| 1. A semiconductor device comprising:
a substrate;
a first device region and a second device region in the substrate;
a gate electrode associated with each device region:
a first semiconductor layer on said substrate in said first device region and having a plane orientation different from that
of the surface of said substrate;
a second semiconductor layer on said substrate in said second semiconductor region and comprised of a strained layer having
the same plane orientation as that of the surface of said substrate;
a thin film cap on the second semiconductor layer effective to enhance the interface between the second semiconductor layer
and the gate electrode,
wherein, said first and second semiconductor layers do not overlap within said first and second device regions.
|