US 7,538,387 B2
Stack SiGe for short channel improvement
Pang-Yen Tsai, Jhu-bei (Taiwan)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (Taiwan)
Filed on Jan. 16, 2007, as Appl. No. 11/653,687.
Claims priority of provisional application 60/878006, filed on Dec. 29, 2006.
Prior Publication US 2008/0157119 A1, Jul. 03, 2008
Int. Cl. H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2006.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01)
U.S. Cl. 257—327  [257/336; 257/344; 257/408; 257/900] 10 Claims
OG exemplary drawing
 
1. A metal-oxide-semiconductor (MOS) device comprising:
a semiconductor substrate;
a gate stack on the semiconductor substrate; and
a stressor having at least a portion in the semiconductor substrate and adjacent the gate stack, wherein the stressor comprises:
a first stressor region having a first impurity concentration;
a second stressor region having a second impurity concentration on the first stressor region; and
a third stressor region having a third impurity concentration on the second stressor region, wherein the second impurity concentration is substantially lower than the first and the third impurity concentrations.