| US 7,538,384 B2 | ||
| Non-volatile memory array structure | ||
| Tzyh-Cheang Lee, Hsinchu (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Shu (Taiwan) | ||
| Filed on Dec. 05, 2005, as Appl. No. 11/294,280. | ||
| Prior Publication US 2007/0126053 A1, Jun. 07, 2007 | ||
| Int. Cl. H01L 29/792 (2006.01) | ||
| U.S. Cl. 257—324 [257/401; 257/E29.309] | 20 Claims |
| 1. A memory device comprising:
a first active region in a substrate;
a second active region in the substrate, the first and second active regions having substantially parallel longitudinal axes;
a plurality of transistors positioned between the first active region and the second active region such that each of the plurality
of transistors utilizes the first active region and the second active region as source/drain regions, each of the plurality
of transistors having a gate electrode, each of the gate electrodes having a rectangular shape and having a longitudinal axis
substantially parallel to the longitudinal axes of the first and second active regions; and
a plurality of word lines, each of the plurality of word lines comprising a separate layer from the gate electrode, each of
the plurality of word lines being electrically coupled to one or more of the gate electrodes.
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