| US 7,538,382 B1 | ||
| Non-volatile two-transistor programmable logic cell and array layout | ||
| Fethi Dhaoui, Patterson, Calif. (US); John McCollum, Saratoga, Calif. (US); Vidyadhara Bellippady, San Jose, Calif. (US); William C. Plants, Campbell, Calif. (US); and Zhigang Wang, Sunnyvale, Calif. (US) | ||
| Assigned to Actel Corporation, Mountain View, Calif. (US) | ||
| Filed on Oct. 29, 2007, as Appl. No. 11/927,237. | ||
| Application 11/927237 is a division of application No. 11/303865, filed on Dec. 16, 2005. | ||
| Application 11/303865 is a continuation in part of application No. 11/155005, filed on Jun. 15, 2005, granted, now 7,285,818, filed on Oct. 23, 2007. | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 29/788 (2006.01) | ||
| U.S. Cl. 257—316 [257/317; 257/321] | 8 Claims |
| 1. An array of non-volatile memory cells including:
a semiconductor body;
at least one memory-transistor well disposed within the semiconductor body;
at least one switch-transistor well disposed within the semiconductor body and electrically isolated from the at least one
memory transistor well;
a plurality of memory transistors formed within the at least one memory-transistor well, each including spaced-apart source
and drain regions;
a plurality of switch transistors formed within the at least one switch-transistor well region, each associated with one of
the memory transistors and including spaced-apart source and drain regions;
a floating gate associated with each memory transistor, each floating gate insulated from and self-aligned with the source
and drain regions of the switch transistor with which it is associated;
a control gate associated with each memory transistor, each control gate disposed above and self aligned with its floating
gate and with the source and drain regions of the at least one switch transistor with which it is associated.
|