| US 7,538,379 B1 | ||
| Non-volatile two-transistor programmable logic cell and array layout | ||
| Fethi Dhaoui, Patterson, Calif. (US); John McCollum, Saratoga, Calif. (US); Vidyadhara Bellippady, Cupertino, Calif. (US); William C. Plants, Campbell, Calif. (US); and Zhigang Wang, Sunnyvale, Calif. (US) | ||
| Assigned to Actel Corporation, Mountain View, Calif. (US) | ||
| Filed on Dec. 16, 2005, as Appl. No. 11/303,865. | ||
| Application 11/303865 is a continuation in part of application No. 11/155005, filed on Jun. 15, 2005, granted, now 7,285,818. | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 29/788 (2006.01) | ||
| U.S. Cl. 257—316 [257/317; 257/321] | 8 Claims |
| 1. A non-volatile memory cell including:
a semiconductor body;
a memory-transistor well disposed within the semiconductor body;
a switch-transistor well disposed within the semiconductor body and electrically isolated from the memory transistor well;
a memory transistor formed within the memory-transistor well and including spaced-apart source and drain regions;
a switch transistor formed within the switch-transistor well and including spaced-apart source and drain regions;
a floating gate insulated from and self aligned with the source and drain regions of the memory transistor and the switch
transistor; and
a control gate disposed above and self aligned with respect to the floating gate and with the source and drain regions of
the memory transistor and the switch transistor.
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