| US 7,538,377 B2 | ||
| Semiconductor memory device | ||
| Yoshihiro Takaishi, Tokyo (Japan) | ||
| Assigned to Elpida Memory, Inc., (Japan) | ||
| Filed on Feb. 14, 2006, as Appl. No. 11/353,257. | ||
| Claims priority of application No. 2005-039217 (JP), filed on Feb. 16, 2005. | ||
| Prior Publication US 2006/0180846 A1, Aug. 17, 2006 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—314 [257/326; 257/261; 257/225; 257/368; 257/381; 438/706; 438/719] | 7 Claims |
| 1. A semiconductor memory device comprising:
a semiconductor substrate having a memory cell array portion;
a plurality of word lines running over the memory cell array portion in a first direction substantially parallel to one another,
each of the word lines being extended over an outside portion of the memory cell array portion;
a plurality of memory cell transistors formed in the memory cell array portion, each of the memory cell transistors having
a gate electrode constituted by a part of an associated one of the word lines and a pair of cell contact pads each formed
between adjacent ones of the word lines; and
a dummy cell contact pad formed over the outside portion of the memory cell array portion and continuously running in a second
direction to cross over each of the word lines, the dummy cell contact pad thereby having portions respectively filling gaps
between adjacent ones of the word lines.
|