| US 7,538,347 B2 | ||
| Thin film transistor having a channel region that includes a plurality of connecting channel regions | ||
| Toru Takeguchi, Tokyo (Japan); and Osamu Miyakawa, Tokyo (Japan) | ||
| Assigned to Mitsubishi Denki Kabushiki Kaisha, Tokyo (Japan) | ||
| Filed on Jun. 12, 2006, as Appl. No. 11/450,332. | ||
| Claims priority of application No. 2005-180994 (JP), filed on Jun. 21, 2005. | ||
| Prior Publication US 2006/0284550 A1, Dec. 21, 2006 | ||
| Int. Cl. H01L 31/00 (2006.01) | ||
| U.S. Cl. 257—59 [257/E27.001] | 6 Claims |
| 1. A thin film transistor comprising:
an insulation substrate;
a semiconductor layer formed on the insulation substrate including,
conductive regions including an impurity, and
a channel region sandwiched between the conductive regions;
an insulation layer that covers the semiconductor layer;
a gate electrode that is formed on the insulator layer at a position opposing the channel region; and
a source electrode and a drain electrode connected to the conductive regions,
wherein the channel region includes a plurality of openings so that a channel that links the conductive regions is divided
into a plurality of connecting channel regions;
the gate electrode covers the openings of the channel region entirely; and
wherein a width of the gate electrode in a direction of a main current flow between the conductive regions is wider than a
width of the openings in the channel regions and the connecting channel regions, so that a channel linking region is formed
in the channel region that lies underneath the gate electrode, and the channel linking region is without impurities doped
therein, and
wherein the semiconductor layer has impurities doped therein in an area other than an area that is underneath the gate electrode.
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