| US 7,538,337 B2 | ||
| Nanowire semiconductor device | ||
| Erwin A. Hijzen, Blanden (Belgium); Erik P. A. M. Bakkers, Heeze (Netherlands); Raymond J. E. Hueting, Hengelo (Netherlands); and Abraham R. Balkenende, Heeze (Netherlands) | ||
| Assigned to NXP B.V., Eindhoven (Netherlands) | ||
| Appl. No. 11/629,657 PCT Filed Jun. 07, 2005, PCT No. PCT/IB2005/051843 § 371(c)(1), (2), (4) Date Dec. 15, 2006, PCT Pub. No. WO2005/124872, PCT Pub. Date Dec. 29, 2005. |
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| Claims priority of application No. 0413310.4 (GB), filed on Jun. 15, 2004. | ||
| Prior Publication US 2008/0029909 A1, Feb. 07, 2008 | ||
| Int. Cl. H01L 29/04 (2006.01); H01L 47/00 (2006.01) | ||
| U.S. Cl. 257—3 [977/700; 977/701; 977/707; 977/720; 977/721; 977/722; 977/723; 977/742; 977/762; 977/938] | 17 Claims |
| 1. A semiconductor device comprising:
a substrate defining opposed first and second major surfaces;
at least one conductive nanowire extending substantially perpendicularly to the major surfaces (4) defining a body region (29) and a drift region (28) along the length of the nanowire (16);
a gate region of conductive material insulated from the nanowires (16) and arranged adjacent to the body region (29) of the nanowires (16) and spaced from the drift region (28) end of the nanowires (16) to control conduction in the nanowires in the body region (29) of the nanowires.
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