providing a substrate, comprising a transistor with a source or a drain formed therein;

forming a bottom dielectric layer with vias therein overlying the substrate, the vias electrically connecting the source or the drain of the transistor;

forming a first dielectric layer with a strip-shaped lower electrode therein overlying the bottom dielectric layer and vias, comprising the steps of:

forming a metal layer on the bottom dielectric layer and the vias;

patterning the metal layer to form the strip-shaped lower electrode;

depositing a first dielectric layer on the strip-shaped lower electrode and the bottom dielectric layer; and

polishing a first dielectric layer, exposing the strip-shaped lower electrode;

forming a second dielectric layer with a phase change layer therein overlying the first dielectric layer and the strip-shaped lower electrode, the phase change layer crossing and contacting the strip-shaped lower electrode at a cross region and the phase change layer is a strip-shaped; and

forming a top electrode, electrically connecting the phase change layer,

wherein the step of patterning the metal layer to form the strip-shaped lower electrode comprises:

forming a patterned photoresist layer on the metal layer, wherein the patterned photoresist layer is strip-shaped;

trimming the patterned photoresist layer to reduce width of the patterned photoresist layer; and

etching the metal layer using the trimmed patterned photoresist layer as a mask to form the strip-shaped lower electrode.