| US 7,538,032 B2 | ||
| Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method | ||
| Robert L. Borwick, Thousand Oaks, Calif. (US); Philip A. Stupar, Oxnard, Calif. (US); Jeffrey F. DeNatale, Thousand Oaks, Calif. (US); Chailun Tsai, Thousand Oaks, Calif. (US); Zhimin J. Yao, Thousand Oaks, Calif. (US); Kathleen Garrett, Woodland Hills, Calif. (US); John White, Lancaster, Calif. (US); Les Warren, Thousand Oaks, Calif. (US); and Morgan Tench, Camarillo, Calif. (US) | ||
| Assigned to Teledyne Scientific & Imaging, LLC, Thousand Oaks, Calif. (US) | ||
| Filed on Jun. 23, 2005, as Appl. No. 11/167,014. | ||
| Prior Publication US 2006/0292866 A1, Dec. 28, 2006 | ||
| Int. Cl. H01L 21/44 (2006.01) | ||
| U.S. Cl. 438—667 [257/E23.067] | 20 Claims |
| 1. A process for fabricating a through-wafer via through a semiconductor wafer on which active circuitry has been fabricated,
the wafer having a first surface and a second surface, comprising:
forming a through-wafer via hole into a semiconductor wafer on which active circuitry has been fabricated;
forming an isolation material directly onto the wafer and onto the interior semiconductor walls of said through-wafer via
hole, said isolation material being electrically insulating, continuous and substantially conformal;
preparing the isolation material for receiving a conductive material such that the conductive material will react with the
isolation material to plate the via; and
depositing conductive material into the via hole over said isolation material such that it is electrically continuous across
the length of said via hole, said conductive material deposited by means of an electroless flowing solution plating process.
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