| US 7,538,027 B2 | ||
| Fabrication method for semiconductor interconnections | ||
| Takashi Onishi, Kobe (Japan); Masao Mizuno, Kobe (Japan); Mikako Takeda, Kobe (Japan); Susumu Tsukimoto, Kyoto (Japan); Tatsuya Kabe, Sakyo-ku (Japan); Toshifumi Morita, Sakyo-ku (Japan); Miki Moriyama, Sakyo-ku (Japan); Kazuhiro Ito, Sakyo-ku (Japan); and Masanori Murakami, Sakyo-ku (Japan) | ||
| Assigned to Kobe Steel, Ltd., Kobe-shi (Japan) | ||
| Filed on Sep. 18, 2006, as Appl. No. 11/532,796. | ||
| Claims priority of application No. 2006-077443 (JP), filed on Mar. 20, 2006. | ||
| Prior Publication US 2007/0218690 A1, Sep. 20, 2007 | ||
| Int. Cl. H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—637 [438/629; 438/638; 438/640; 438/668] | 17 Claims |
| 1. A method for fabricating semiconductor interconnections of a Cu-alloy embedded in respective recesses provided in an insulating
film on a semiconductor substrate, said method comprising the steps of:
forming the respective recesses having a minimum width not more than 0.15 μm, and a ratio of a depth thereof to the minimum
width (a depth/minimum width ratio) not less than 1;
forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective
recesses; and
subsequently, annealing the Cu-alloy film to not lower than 200° C., and pressurizing the Cu-alloy film to not less than 50
MPa to thereby embed the Cu-alloy film into the respective recesses.
|