| US 7,538,026 B1 | ||
| Multilayer low reflectivity hard mask and process therefor | ||
| Kouros Ghandehari, Santa Clara, Calif. (US); Anna M. Minvielle, San Jose, Calif. (US); Marina V. Plat, San Jose, Calif. (US); and Hirokazu Tokuno, Cupertino, Calif. (US) | ||
| Assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif. (US) | ||
| Filed on Apr. 04, 2005, as Appl. No. 11/98,262. | ||
| Int. Cl. H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—636 [257/E21.495] | 23 Claims |
| 1. A method of forming a hard mask for an integrated circuit, the method comprising steps of:
providing an oxide layer above a gate conductor layer and a substrate and etching the oxide layer before etching the gate
conductor layer;
providing a dual layer anti-reflective coating above the oxide layer, the dual layer anti-reflective coating including at
least silicon rich nitride applied to the oxide layer, wherein the dual layer anti-reflective coating and the oxide layer
are provided above the gate conductor layer;
providing a photoresist layer above the dual layer anti-reflective coating;
patterning the photoresist layer to form a photoresist feature; and
selectively removing the dual layer anti-reflective coating in accordance with the photoresist feature.
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