| US 7,538,025 B2 | ||
| Dual damascene process flow for porous low-k materials | ||
| Chao-Cheng Chen, Chong-Ling (Taiwan); Chen-Nan Yeh, Hsi-chi (Taiwan); and Chien-Chung Fu, Sanchong (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Company, Hsin-Chu (Taiwan) | ||
| Filed on Nov. 14, 2003, as Appl. No. 10/714,304. | ||
| Prior Publication US 2005/0106856 A1, May 19, 2005 | ||
| Int. Cl. H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—636 [438/634; 257/E21.579] | 39 Claims |
| 1. A method of forming a dual damascene opening, comprising the steps of:
providing a structure having an overlying exposed conductive layer formed thereover;
forming a dielectric layer over the exposed conductive layer;
forming an anti-reflective coating layer over the dielectric layer;
etching the anti-reflective layer and the dielectric layer using a via opening process to form an initial via exposing a portion
of the conductive layer;
forming a protective film portion over at least the exposed portion of the conductive layer, the protective film portion being
comprised of the elements C and H; and
patterning the anti-reflective coating layer and the dielectric layer to reduce the initial via to a reduced via and to form
a trench opening substantially centered over the reduced via; the trench opening and the reduced via comprising the dual damascene
opening, wherein the structure includes a silicon substrate or a germanium substrate; the conductive layer is comprised of
copper, aluminum, gold or silver; the dielectric layer is comprised of the elements Si, O, C and/or H such as SiOCH; and the
anti-reflective coating layer is comprised of SiON or SiOC.
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