| US 7,538,002 B2 | ||
| Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors | ||
| Da Zhang, Austin, Tex. (US); Vance H. Adams, Austin, Tex. (US); Bich-Yen Nguyen, Austin, Tex. (US); and Paul A. Grudowski, Austin, Tex. (US) | ||
| Assigned to Freescale Semiconductor, Inc., Austin, Tex. (US) | ||
| Filed on Feb. 24, 2006, as Appl. No. 11/361,171. | ||
| Prior Publication US 2007/0202651 A1, Aug. 30, 2007 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—296 [438/199; 438/239; 438/253; 438/259; 257/E21.431; 257/E21.438] | 20 Claims |
| 1. A semiconductor fabrication process, comprising:
forming first and second isolation structures laterally positioned on either side of a transistor region of a semiconductor
layer;
forming a gate structure overlying a portion of the transistor region, wherein the gate structure includes an electrically
conductive gate electrode overlying a gate dielectric layer overlying the semiconductor layer, and further wherein sidewalls
of the gate electrode define boundaries of a channel region underlying the gate structure and source/drain regions on either
side of the channel region extending between the channel region and the first and second isolation structures;
removing portions of the semiconductor layer in the source/drain regions to form source/drain recesses;
removing upper portions of the first and second isolation structures to form first and second recessed isolation structures,
wherein a lower surface of the source/drain recesses and an upper surface of the first and second recessed isolation structures
are vertically displaced below an upper surface of the semiconductor substrate by a first displacement and a second displacement
respectively, wherein the first displacement is greater than the second displacement; and
filling the source/drain recesses with a source/drain stressor.
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