| US 7,537,977 B2 | ||
| Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films | ||
| Woon-Yong Park, Suwon (Korea, Republic of); and Bum-Ki Baek, Suwon (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Mar. 09, 2007, as Appl. No. 11/716,228. | ||
| Application 11/716228 is a division of application No. 11/233038, filed on Sep. 23, 2005, granted, now 7,202,502. | ||
| Application 10/627752 is a division of application No. 09/968522, filed on Oct. 02, 2001, granted, now 6,621,545, filed on Sep. 16, 2003. | ||
| Application 09/968522 is a division of application No. 09/417045, filed on Oct. 12, 1999, granted, now 6,335,276, filed on Jan. 01, 2002. | ||
| Application 11/233038 is a continuation of application No. 10/627752, filed on Jul. 28, 2003, abandoned. | ||
| Claims priority of application No. 1998-50880 (KR), filed on Nov. 26, 1998; and application No. 1999-5828 (KR), filed on Feb. 22, 1999. | ||
| Prior Publication US 2007/0152224 A1, Jul. 05, 2007 | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 438—149 [438/151; 438/148] | 3 Claims |
| 1. A thin film transistor (TFT) array panel, comprising:
a substrate;
a gate wire formed on the substrate and including a gate line, a gate electrode and a gate pad;
a gate insulating layer pattern formed on the gate wire and having a contact hole exposing the gate pad;
a semiconductor layer pattern formed on the gate insulating layer pattern;
an ohmic contact layer pattern formed on the semiconductor layer pattern;
a data wire formed on the ohmic contact layer pattern, including a data line, a source electrode, a drain electrode and a
data pad;
a passivation layer pattern formed on the data wire, having contact holes exposing the gate pad, the data pad and the drain
electrode; and
a pixel electrode electrically connected to the exposed portion of the drain electrode,
wherein the ohmic contact layer pattern includes a portion disposed under the data pad and having a planar shape substantially
the same as that of the data pad due to simultaneous etching and wherein the contact hole of the passivation layer, exposing
the gate pad coincide with the contact hole of the gate insulating layer due to simultaneous etching.
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