| US 7,537,973 B2 | ||
| Method for fabricating structure of thin film transistor array | ||
| Yu-Cheng Chen, Hsinchu (Taiwan) | ||
| Assigned to Industrial Technology Research Institute, Hsinchu (Taiwan) | ||
| Filed on Jun. 08, 2006, as Appl. No. 11/309,009. | ||
| Claims priority of application No. 95101181 A (TW), filed on Jan. 12, 2006. | ||
| Prior Publication US 2007/0161160 A1, Jul. 12, 2007 | ||
| Int. Cl. H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 21/336 (2006.01); H01L 21/8234 (2006.01) | ||
| U.S. Cl. 438—149 [438/153; 438/257; 438/197] | 14 Claims |
| 1. A method for fabricating a TFT array, comprising:
providing a substrate having a gate electrode layer, a gate insulating layer and a silicon layer formed thereon;
patterning the gate electrode layer, the gate insulating layer and the silicon layer to define a gate area, a gate line and
a gate line wiring area;
forming a passivation layer on the whole substrate;
patterning the passivation layer to form at least two contact holes in the passivation layer over the silicon layer of the
gate area, and to remove a portion of the passivation layer above the gate line and the passivation layer above the gate line
wiring area;
forming an ion implanting layer and a metal layer on the whole substrate;
patterning the ion implanting layer and the metal layer to form a source region, a drain region, a data line, a data line
wiring area and a second layer of the gate line wiring area; and
forming a pixel electrode on the passivation layer, wherein the pixel electrode is electrically coupled to the drain region.
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