| US 7,535,257 B2 | ||
| Receiver circuit, interface circuit, and electronic instrument | ||
| Yukinari Shibata, Sapporo (Japan); Nobuyuki Saito, Sapporo (Japan); Tomonaga Hasegawa, Sapporo (Japan); and Takuya Ishida, Sapporo (Japan) | ||
| Assigned to Seiko Epson Corporation, Tokyo (Japan) | ||
| Filed on Sep. 07, 2004, as Appl. No. 10/934,529. | ||
| Claims priority of application No. 2003-314055 (JP), filed on Sep. 05, 2003; application No. 2004-014412 (JP), filed on Jan. 22, 2004; and application No. 2004-065938 (JP), filed on Mar. 09, 2004. | ||
| Prior Publication US 2005/0088218 A1, Apr. 28, 2005 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03K 19/0175 (2006.01) | ||
| U.S. Cl. 326—82 [326/86; 327/108; 327/544] | 24 Claims |
| 1. A receiver circuit connected with a transmitter circuit through differential signal lines, the receiver circuit comprising:
a current/voltage conversion circuit that performs a current/voltage conversion based on current that flows through the differential
signal lines and outputs first and second voltage signals that form differential voltage signals;
a comparator that compares the first and second voltage signals and outputs an output signal;
a power-down detection circuit that, when the transmitter circuit transmits a power-down command by driving the differential
signal lines in a normal transfer mode, detects the transmitted power-down command based on a comparison result from the comparator;
and
a power-down setting circuit that sets at least one of the current/voltage conversion circuit and the comparator to a power-down
mode when the power-down detection circuit detects the power-down command.
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