| US 7,534,682 B2 | ||
| Semiconductor memory device with a stacked gate including a floating gate and a control gate and method of manufacturing the same | ||
| Fumitaka Arai, Yokohama (Japan); Yasuhiko Matsunaga, Kawasaki (Japan); and Makoto Sakuma, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Oct. 16, 2006, as Appl. No. 11/582,015. | ||
| Application 11/582015 is a division of application No. 11/061824, filed on Feb. 18, 2005, granted, now 7,122,866. | ||
| Claims priority of application No. 2004-080809 (JP), filed on Mar. 19, 2004. | ||
| Prior Publication US 2007/0034934 A1, Feb. 15, 2007 | ||
| Int. Cl. H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01) | ||
| U.S. Cl. 438—257 [438/275; 438/279; 438/201] | 14 Claims |
| 1. A method of fabricating a semiconductor memory device comprising:
forming a first insulating film on a semiconductor substrate;
patterning the first insulating film to leave the first insulating film on a first and a second element region;
etching the semiconductor substrate by use of the first insulating film as a mask to make a plurality of trenches in the semiconductor
substrate;
etching the side face of the first insulating film on the second element region, while protecting the first insulating film
on the first element region;
forming a second insulating film on the semiconductor substrate to fill the trenches;
etching the second insulating film by use of the first insulating film as a stopper;
removing the first insulating film so as to form a first and a second element isolating region with which the trenches are
filled and the upper parts of which project from the surface of the semiconductor substrate and enclose the first and second
element regions respectively;
forming a first gate insulating film on the first and second element regions;
removing the first gate insulating film on the second element region, while protecting the first gate insulating film on the
first element region and the first element isolating region;
forming on the second element region a second gate insulating film thinner than the first gate insulating film, while protecting
the first gate insulating film on the first element region; and
forming gate electrodes on the first and second gate insulating films.
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