| US 7,534,675 B2 | ||
| Techniques for fabricating nanowire field-effect transistors | ||
| Sarunya Bangsaruntip, Mount Kisco, N.Y. (US); Guy Moshe Cohen, Mohegan Lake, N.Y. (US); and Katherine Lynn Saenger, Ossining, N.Y. (US) | ||
| Assigned to International Business Machiens Corporation, Armonk, N.Y. (US) | ||
| Filed on Sep. 05, 2007, as Appl. No. 11/850,644. | ||
| Prior Publication US 2009/0061568 A1, Mar. 05, 2009 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—197 [438/178; 977/720; 977/742; 977/762; 977/938; 257/E23.141; 257/E21.177] | 13 Claims |
| 1. A method of fabricating a field-effect transistor (FET), the method comprising the steps of:
providing a substrate having a silicon-on-insulator (SOI) layer;
depositing at least one nanowire over the SOI layer;
forming a sacrificial gate over the SOI layer so as to cover a portion of the nanowire that forms a channel region;
selectively growing an epitaxial semiconductor material from the SOI layer that covers the nanowire and attaches the nanowire
to the SOI layer in a source region and in a drain region;
removing the sacrificial gate;
forming an oxide that divides the SOI layer into at least two electrically isolated sections, one section included in the
source region and the other section included in the drain region;
forming a gate dielectric layer over the channel region;
forming a gate over the channel region separated from the nanowire by the gate dielectric layer; and
forming a metal-semiconductor alloy over the source and drain regions.
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