| US 7,533,359 B2 | ||
| Method and system for chip design using physically appropriate component models and extraction | ||
| Louis K. Scheffer, Campbell, Calif. (US); and Joel R. Phillips, Sunnyvale, Calif. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on May 19, 2006, as Appl. No. 11/437,583. | ||
| Claims priority of provisional application 60/683428, filed on May 20, 2005. | ||
| Prior Publication US 2006/0265680 A1, Nov. 23, 2006 | ||
| Int. Cl. G06F 17/50 (2006.01); G06F 19/00 (2006.01) | ||
| U.S. Cl. 716—5 [700/98; 700/110; 700/120; 700/121] | 29 Claims |
| 1. A method for extracting transistor parameters from an IC layout, comprising:
receiving a proposed IC layout, the proposed IC layout including a transistor;
receiving a model of a proposed manufacturing process, wherein the model of the proposed manufacturing process is used to
approximate a variation of an actual profile of the transistor caused by the proposed manufacturing process; and
evaluating, based on the proposed IC layout and the model of the proposed manufacturing process, an effect of the proposed
manufacturing process on one or more parameters of the transistor, wherein the act of evaluating is performed by a processor.
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