| US 7,533,358 B2 | ||
| Integrated sizing, layout, and extractor tool for circuit design | ||
| Prakash Gopalakrishnan, Allison Park, Pa. (US); and Hongzhou Liu, Pittsburgh, Pa. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Oct. 12, 2006, as Appl. No. 11/580,637. | ||
| Prior Publication US 2008/0104557 A1, May 01, 2008 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—4 [716/9; 716/10; 716/13; 716/14] | 21 Claims |
| 1. A method for designing a circuit, wherein the circuit comprises a group of devices, comprising:
initializing a set of design points, wherein a design point comprises a design of the circuit that meets a set of predefined
design specifications;
determining sizes for the group of devices using a size optimization iteration process;
pausing the sizing optimization iteration process periodically for updating parasitic information of the circuit;
selecting a subset of design points from the set of design points;
generating a layout of the circuit using device sizes obtained from the set of design points;
generating an extracted netlist using the layout, wherein the extracted netlist includes parasitic information of the circuit;
simulating the circuit using the extracted netlist to verify the set of predefined design specifications are met.
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