| US 7,533,317 B2 | ||
| Serializer/deserializer circuit for jitter sensitivity characterization | ||
| Dominique P Bonneau, La Rochelle (France); Philippe Hauviller, Itteville (France); and Vincent Vallet, Mennety (France) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Oct. 06, 2006, as Appl. No. 11/583,048. | ||
| Application 11/583048 is a division of application No. 10/707961, filed on Jan. 28, 2004, granted, now 7,251,764. | ||
| Claims priority of application No. 03368048 (EP), filed on May 27, 2003. | ||
| Prior Publication US 2007/0088998 A1, Apr. 19, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—733 [714/700; 714/738; 714/744] | 1 Claim |
| 1. A method of characterizing jitter sensitivity in a serializer/deserializer (SERDES) circuit having built-in self test (BIST)
capabilities, the method comprising:
providing a clock and data recovery (CDR) circuit coupled to said SERDES circuit that generates recovered clock and data from
an incoming serial data stream;
generating from a deserializer circuit connected to said CDR circuit corresponding data (Parallel Data Out) and clock (DES
clock) in a parallel format;
generating BIST patterns from a programmable pattern generator;
receiving either the BIST patterns or input data (Parallel Data In) in a parallel format on a data input of a serializer circuit
and generating a serial data stream from an external clock (SER clock) on a clock input of the serializer circuit;
adding a perturbation delay to said serial data stream to produce a perturbed serial data stream;
outputting either the serial data stream or the perturbed serial data stream in a loop back to the CDR circuit; and
detecting a start-of-frame pattern using a dedicated signal (FD).
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