| US 7,533,316 B2 | ||
| Method and apparatus for disabling and swapping cores in a multi-core microprocessor | ||
| Ray Ramadorai, Beaverton, Oreg. (US); Derek Feltham, Portland, Oreg. (US); and Jonathan Douglas, Portland, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Mar. 31, 2006, as Appl. No. 11/394,737. | ||
| Prior Publication US 2007/0255985 A1, Nov. 01, 2007 | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—733 [714/30] | 9 Claims |
| 1. An electronic appliance, comprising:
a memory to store data;
a network controller to communicate data; and
a multi-core processor to process data coupled with the network controller and the memory, wherein the processor includes
circuitry to disable one or more cores and function with the remaining core(s).
|